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SEMICONDUCTOR TECHNICAL DATA
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Designer'sTM Data Sheet
TMOS E-FET.TM High Energy Power FET
N-Channel Enhancement-Mode Silicon Gate
This advanced TMOS power FET is designed to withstand high energy in the avalanche mode and switch efficiently. This new high energy device also offers a gate-to-source zener diode designed for 4 kV ESD protection (human body model). * * * * * ESD Protected 4 kV Human Body Model 400 V Machine Model Avalanche Energy Capability Internal Source-To-Drain Diode Designed to Replace External Zener Transient Suppressor-Absorbs High Energy in the Avalanche Mode
G
MTP12N06EZL
TMOS POWER FET 12 AMPERES 60 VOLTS RDS(on) = 0.180 OHM
(R)
D
S
CASE 221A-06, Style 5 TO-220AB
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-Source Voltage Drain-Gate Voltage (RGS = 1.0 M) Gate-Source Voltage -- Continuous Gate-Source Voltage -- Non-Repetitive (tp 10 ms) Drain Current -- Continuous -- Continuous @ 100C -- Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy -- Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 12 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance -- Junction to Case -- Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS RJC RJA TL Value 60 60 15 20 12 7.1 36 45 0.36 - 55 to 150 72 2.78 62.5 260 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ C/W C
Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.
E-FET and Designer's are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
(c) Motorola TMOS Motorola, Inc. 1995
Power MOSFET Transistor Device Data
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MTP12N06EZL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Source Breakdown Voltage (VDS = 0 V, IG = 10 mA) Gate-Body Leakage Current (VGS = 10 Vdc, VDS = 0 V, TJ = 25C) (VGS = 10 Vdc, VDS = 0 V, TJ = 150C) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static Drain-Source On-Resistance (VGS = 5.0 Vdc, ID = 6.0 Adc) Drain-Source On-Voltage (VGS = 5.0 Vdc) (ID = 12 Adc) (ID = 6.0 Adc, TJ = 125C) Forward Transconductance (VDS = 8.0 Vdc, ID = 6.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (See Figures 8 & 9) (VDS = 48 Vdc, ID = 12 Adc, VGS = 5.0 Vdc) (VDS = 30 Vdc, ID = 12 Adc, VGS = 5.0 Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (1) (IS = 12 Adc, VGS = 0 Vdc) (IS = 12 Adc, VGS = 0 Vdc, TJ = 125C) VSD -- -- trr (IS = 12 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature. LD LS -- -- 4.5 7.5 -- -- nH nH ta tb QRR -- -- -- -- 1.1 1.05 325 124 201 2.013 1.4 -- -- -- -- -- C ns Vdc -- -- -- -- -- -- -- -- 70 436 158 186 10.6 1.4 5.9 6.0 90 540 380 340 40 -- -- -- nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss -- -- -- 430 224 51 600 310 100 pF VGS(th) 1.0 -- RDS(on) VDS(on) -- -- gFS 3.0 -- -- 6.8 2.6 2.3 -- mhos -- 1.5 4.0 -- 2.0 -- 0.18 Vdc mV/C Ohm Vdc IGSS -- -- -- -- 500 100 nAdc Adc V(BR)DSS 60 -- IDSS -- -- 18 -- -- -- 10 100 -- Vdc -- 0.06 -- -- Vdc mV/C Adc Symbol Min Typ Max Unit
Reverse Recovery Time (See Figure 14)
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Motorola TMOS Power MOSFET Transistor Device Data
MTP12N06EZL
TYPICAL ELECTRICAL CHARACTERISTICS
24 TJ = 25C I D , DRAIN CURRENT (AMPS) 18 VGS = 10 V 8V 6V 24 7V I D , DRAIN CURRENT (AMPS) 5V 18 TJ = - 55C 25C 12 100C 6 VDS 10 V
12 4V 6
0 0 0.5 1 1.5 2 2.5 3 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
0 2 2.5 3 3.5 4 4.5 5 5.5 6 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.15 0.13
VGS = 5 V TJ = 100C
0.096
TJ = 25C
0.092 VGS = 10 V 0.088
0.11 25C
0.09
0.07
0.084
15 V
- 55C
0.05 0 6 12 ID, DRAIN CURRENT (AMPS) 18 24
0.08
0
6
12 ID, DRAIN CURRENT (AMPS)
18
24
Figure 3. On-Resistance versus Drain Current and Temperature
Figure 4. On-Resistance versus Drain Current and Gate Voltage
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 - 50 - 25 0 25 50 75 100 125 150 VGS = 5 V ID = 12 A I DSS , LEAKAGE (nA)
100 VGS = 0 V TJ = 125C
10
100C
25C 1
0
10
20
30
40
50
60
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
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MTP12N06EZL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1200 VDS = 0 V 1000 C, CAPACITANCE (pF) 800 600 400 200 Crss 0 0 5 10 15 20 25 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Ciss Coss TJ = 25C
The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
Figure 7. Capacitance Variation
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Motorola TMOS Power MOSFET Transistor Device Data
MTP12N06EZL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 6 QT 5 4 3 2 1 0 0 2 Q3 4 6 QT, TOTAL CHARGE (nC) 8 VDS Q1 Q2 VGS 50 40 30 ID = 12 A TJ = 25C 20 10 0 10 60 1000 VDD = 30 V ID = 12 A VGS = 5 V TJ = 25C t, TIME (ns) tr tf td(off) 100 td(on) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)
10 1 10 RG, GATE RESISTANCE (OHMS) 100
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
12 10 I S , SOURCE CURRENT (AMPS) 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) VGS = 0 V TJ = 25C
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain- to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
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MTP12N06EZL
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 1 ms 10 ms dc 100 s E , SINGLE PULSE DRAIN-TO-SOURCE AS AVALANCHE ENERGY (mJ) VGS = 20 V SINGLE PULSE TC = 25C 10 10 s 75 ID = 12 A 60
45
30
1
RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT
15 0
0.1 0.1 1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100
25
50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)
150
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.02 0.01 SINGLE PULSE t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01 t1 0.05 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)
0.01 1.0E-05
1.0E-04
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
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Motorola TMOS Power MOSFET Transistor Device Data
MTP12N06EZL
PACKAGE DIMENSIONS
-T- B
4
SEATING PLANE
F T S
C
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 --- --- 0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 --- --- 2.04
Q
123
A U K
STYLE 5: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN
H Z L V G D N R J
CASE 221A-06 ISSUE Y
Motorola TMOS Power MOSFET Transistor Device Data
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MTP12N06EZL
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
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Motorola TMOS Power MOSFET Transistor Device Data MTP12N06EZL/D

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